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STP402 - MIT LL Superconductor Electronics Fabrication Process for VLSI Circuits With 4, 8, and 10 Niobium Layers (Annotated slide presentation)

MIT LL Superconductor Electronics Fabrication Processes for VLSI circuits with
4, 8, and 10 Niobium Layers

Sergey K. Tolpygo, V. Bolkhovsky, T. Weir, W.D. Oliver,
L.M. Johnson, and M.A. Gouker

Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA 02420

Abstract  We present a review of superconductor electronics fabrication processes developed at MIT Lincoln Laboratory for very large scale integrated (VLSI) circuits with 4, 8, and 10 Nb metal layers and Nb/Al-AlOx/Nb Josephson junctions (JJs). The processes utilize 248-nm photolithography and chemical mechanical polishing of SiO2 interlayer dielectric for planarization of all layers. The current process node offers minimum feature size of 350 nm for Nb wiring layers, Josephson junctions with critical current density of 10 kA/cm2 (100 µA/µm2) and minimum size of 700 nm. The process salient features and characterization is given and our roadmap to achieving circuit densities of 106 JJs per cm2 and beyond is discussed.

This work was sponsored by the IARPA under Air Force Contract FA872105C0002. Opinions, interpretations, conclusions, and recommendations are those of the authors, and not necessarily endorsed by the United States Government.

Keywords (Index Terms)   superconductor electronics, superconducting integrated circuit, Josephson junction, Nb/Al-AlOx/Nb tunnel junction, superconductor electronics fabrication, RQL, RSFQ, ERSFQ

IEEE/CSC & ESAS SUPERCONDUCTIVITY NEWS FORUM (global edition), October 2014.
Received September 17, 2014; Accepted September 19, 2014.  Reference STP402; Category 4.
This invited presentation 1EOr2A-01 was given at the ASC 2014.  A manuscript was not submitted to ASC.