SNF Issue No. 43, February 2018
Rebooting Computing Week 2017 Impressions
By D. Scott Holmes, SNF Co-editor Electronics
Rebooting Computing Week (November 6-10, 2017) included three related meetings focusing on the next era of computing. This year superconductor electronics, while still far from central, was noticeably present and actively discussed. Links to videos from the meetings are available here.
Nov. 6-7 International Roadmap for Devices and Systems (IRDS) Fall Conference
The International Technology Roadmap for Semiconductors (ITRS) projected technology requirements and potential solutions for semiconductors from 2001 to 2014. The ITRS used transistor feature sizes, density, clock rate, and other metrics to roadmap the future of integrated circuits. In 2015, the ITRS committee presented a new roadmap, called ITRS 2.0, for key systems that contain integrated circuits and drive process, design, and integration technologies. Subsequent partnering of ITRS 2.0 with the IEEE Rebooting Computing (IEEE RC) Initiative resulted in the International Roadmap for Devices and Systems (IRDS).
Superconductor Electronics Fabrication Process with MoNx Kinetic Inductors and Self-Shunted Josephson Junctions
THERE has been a continuing progress in superconductor electronics fabrication towards increasing the number of superconducting layers and reducing the minimum size of circuit features -. A breakthrough into a very large scale integration (VLSI) of superconducting digital circuits has recently been made as a result. For instance, single flux quantum (SFQ) circuits containing close to one million Josephson junctions (JJs) and having circuit density over 1.3∙106 JJs per cm2 have been demonstrated , using the 350-nm fabrication process SFQ5ee developed at MIT Lincoln Laboratory (MIT LL) . This process utilizes resistively shunted Nb/AlOx"Al/Nb Josephson junctions with critical current density Jc = 0.1 mA/μm2 and geometrical inductors formed on multiple superconducting wiring layers of niobium. Currently, it is perhaps the most advanced fabrication process for superconductor electronics, with a theoretical maximum circuit density of about 4∙106 JJs per cm2 ,. However, further increase of the integration scale of SFQ circuits is challenging because of the large area of individual SFQ cells, mainly determined by the area of JJ shunt resistors and geometrical inductors .
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