Paper
STP720
1EOr2B-02

Lowering Latency in High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using Interleaved Register File

Volume Number:
17
Issue Number:
52
Akira Fujimaki, Ryota Kashima, Ikki Nagaoka, Tomoki Nakano Masamitsu Tanaka, Taro Yamashita

paper Menu