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Invited

STP-720

1EOr2B-02

Lowering Latency in High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using Interleaved Register File

Akira Fujimaki, Ryota Kashima, Ikki Nagaoka, Tomoki Nakano Masamitsu Tanaka, Taro Yamashita

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Paper

Slides

Fujimaki presentation.pdf (1.5 MB)

Date

8 March 2023

Series

SNF Issue 52, March 2023

ASC 2022

Presentation Category

Electronics

Topics

Cryogenic Electronics

Quantum Computing

Josephson Junction

Digital

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SNF Issue No. 63, March 2026

Lowering Latency in High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using Interleaved Register File

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Upcoming Events

The 17th IEEE Workshop on Low-Temperature Electronics

10th International Workshop on Numerical Modelling of High Temperature Superconductors

Current SNF Issue

SNF Issue No. 63, March 2026

SNF Issue No. 63, March 2026

Lowering Latency in High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using Interleaved Register File

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